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AMS Design Verification Intern

Analogdevices

Assago · Posted Oct 21

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At a glance

Location
Assago, Italy
Work type
Onsite
Category
Design

AMS Design Verification Intern in Milan, Italy. Internship focused on analog/mixed-signal design verification using Verilog-AMS and SystemVerilog, with opportunities to design specifications, create verification plans, model analog blocks, run AMS simulations, verify state machines with SystemVerilog analog assertions, and build metric-driven verification environments (UVM/DMS/AMS).

What they are looking for

Verilog-amsSystemverilogUvmAmsAnalog-mixed-signal

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