6-month contract in Marvell's office in Pavia, Italy, for an Analog IC Design Engineer Intern; exposure to Cadence tools and advanced CMOS processes (3nm FinFET and 2nm GAAFET); potential sponsorship for an Industrial Master Thesis; work on AI and Cloud data center applications.
What they are looking for
Details
- Work type
- Onsite
- Compensation
- Paid
- Remote eligible
- No
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