Internship in NVIDIA's SOC group (Shanghai, CN) focusing on RTL design and verification of SysASIC and clock-related IPs. Responsibilities include developing Verilog/SystemVerilog RTL, testbenches, assertions, and debugging across simulation, formal verification, lint, CDC/RDC, and synthesis. Pursuing a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field; familiarity with Verilog/SystemVerilog; UVM/SVA knowledge; Linux development environment experience preferred.
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