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ASIC Design Engineer I (Intern) - United States

Cisco

San Jose · Posted Oct 15

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At a glance

Location
San Jose, CA
Work type
Onsite
Category
Engineering

ASIC Design Engineer Intern located in San Jose, CA. The role involves participating in design specifications, Verilog RTL implementation, full chip integration, functional coverage, collaboration with verification and physical design teams, and post-silicon validation. Minimum qualifications include undergraduate enrollment in ASIC design or related field with knowledge of Verilog/SystemVerilog.

What they are looking for

VerilogSystemverilogPythonPerlTcl

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