ASIC Design Engineer Intern at Ambarella, focused on designing and implementing video compression, image processing, neural network and AI accelerator logic, and processor cores using Verilog/SystemVerilog. Responsibilities include RTL synthesis/optimization, test-benches/verification (SystemVerilog, UVM, C++, Perl), and chip bring-up/testing. Requires a Master’s in Electrical/Electronics/Computer Engineering (0-5 years) with knowledge of Verilog/SystemVerilog, Perl, and design verification.
What they are looking for
Details
- Work type
- Onsite
- Remote eligible
- No
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