ASIC Design Engineer (RDSS Intern) – Multimedia IP team in Taiwan. Responsibilities include IP level front-end design, collaboration with design verification engineers, analyze build trade-offs, and deliverables. Requires Master's Degree in EE, CS or CE or equivalent, proficiency with Verilog and SystemVerilog, AI Agent and AI-enabled automation workflows, and ability to work independently in a fast-paced environment.
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