ASIC Design Engineer (RDSS Intern) in NVIDIA's Multimedia IP team in Taiwan (Hsinchu). Responsibilities include IP front-end design, collaboration with verification engineers, analyzing build trade-offs, and delivering task lists. Requirements include a Master's degree (EE/CS/CE or equivalent), digital build coursework, IC build experience, and proficiency in Verilog and SystemVerilog, plus AI-enabled automation workflows. Stand-out skills include C++/SystemC modeling and scripting in Python, Perl, tcl, Make, and Shell.
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