Chip Level Defect Localization and Failure Analysis Engineer - RDSS Intern

Location: Taiwan, Hsinchu

By submitting your resume, you’re expressing interest in our 2027 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with the local district office before applying for the role.

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We are looking for a skilled, creative, and highly motivated RDSS Intern in the field of Electrical Failure Analysis to join the electro-optical FA team in Hsinchu, TW.

What you'll be doing

Your main job will be to perform electro-optical failure analysis including Photon-Emission, Laser-Voltage-Probing and Soft-Defect-Localization (aka SDL, LADA...) to support product development, design-debug, yield-ramp, reliability and customer return analysis of advanced flip chip devices manufactured in the most advanced CMOS technology.

The work requires in-depth understanding of scan-chain based logical test. Based on production test results (e.g. error-logs, flop mapping and SW-diagnosis) you will narrow down the logically failing area with the goal of locating the one failing FET or cell out of the whole chip.

Most analyses will require you to setup test-loops within our Advantest 93k tester SW. Additionally, you will use CAD layout tools for in-chip navigation and circuit simulation tools to aid your analysis. The goal is that our EFA results enable different Physical FA teams local and abroad to find the actual physical root-cause. Based on our work and the resulting PFA findings, our Foundry partners can improve their process technology and increase our product yield and reliability.

You will need basic Unix skills because the CAD, circuit simulation tools and 93k tester SW are all run in a Unix environment.

Design-debug and more complicated defect localizations will often require you working in multi-functional teams (e.g. with Design for Test, Test-Engineers and Product-Engineers, sometimes around the globe..) including presenting & explaining your results. To guide such team and PFA efforts you will need deep understanding of transistor physics, the CMOS fabrication processes and PFA tools/techniques such as SEM, TEM, FIB & AFM.

Support Die Probe Package second-source development for A16 FA readiness.

What we need to see

Master's or PhD degree in Electrical/Computer Engineering or other related field

Basic understanding of DFT for large-scale logical test (scan-chain based structural and at-speed testing and basics of test compression).

Experience working in a lab, setting up and debugging test environments. / Functional knowledge of transistor device physics & advanced CMOS manufacturing processes. / Test bring-up in the Advantest 93k test environment.

Knowledge of CAD layout tools, logic circuit simulation tools and Unix operating system. / Software languages that may be of use include PERL, TCL, C++, STYLE.

Good written and verbal communication skills are critical.