As a DFT Intern at Etched, you will review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. This 12-week paid internship is based at our San Jose, CA office.
What they are looking for
Verilog
Systemverilog
Python
Tcl
Dft
Details
- Work type
- Onsite
- Compensation
- Paid
- Remote eligible
- No
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