Fellow, AI-Native Networking Silicon Systems

Location: Santa Clara, California, United States Department: Engineering

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE

AMD is seeking a Fellow to lead the development of next-generation AI-native methodologies for silicon architecture, RTL generation, verification automation, and design optimization. This highly technical leadership role combines deep networking and ASIC architecture expertise with AI systems and scalable software infrastructure to transform field-proven programmable architectures into optimized fixed-function silicon. The Fellow will define strategy and drive innovation across AMD networking and infrastructure programs, influencing architecture, methodology, tooling, and engineering productivity.

THE PERSON

The ideal candidate is a recognized technical leader in networking and silicon architecture with deep expertise across ASIC design, programmable packet processing, verification, and AI-assisted engineering. This individual will work across hardware and software organizations to establish new methodologies, influence technology strategy, and scale AI-enabled silicon development.

KEY RESPONSIBILITIES

Define and lead AI-assisted methodologies for generating synthesizable RTL from high-level architectural specifications and programmable packet-processing pipelines.

Develop automated techniques to optimize pipeline organization, lookup structures, memories, and datapaths for power, performance, area, and cost.

Drive AI-assisted hardware architecture exploration, implementation, and design optimization.

Lead automated verification generation, including reference models, testbenches, assertions, coverage plans, and regression environments.

Establish methodologies to prove functional equivalence between programmable and generated implementations using simulation, formal verification, and differential testing.

Provide technical leadership across networking silicon, packet processing, telemetry, forwarding architectures, NoC technologies, and infrastructure acceleration.

Guide architectural tradeoffs across multiple ASIC programs and influence future networking IP, Enterprise NIC, DPU, and embedded networking architectures.

Define reusable AI frameworks and scalable software infrastructure for architecture, design, verification, debug, and optimization workflows.

Influence AMD's broader AI-enabled engineering strategy and drive improvements in engineering productivity across silicon development.

PREFERRED EXPERIENCE

Deep technical expertise in networking, ASIC architecture, silicon design, verification, or related hardware domains.

Strong expertise in networking architectures, packet processing, forwarding, telemetry, programmable silicon, NoC, NIC/DPU, and infrastructure acceleration.

Experience with RTL generation, hardware architecture exploration, PPA optimization, simulation, formal verification, differential testing, and functional equivalence.

Experience developing or deploying AI-assisted engineering methodologies and large-scale design or verification automation.

Proven ability to lead complex, cross-disciplinary initiatives spanning hardware, software, AI, and engineering infrastructure.

Demonstrated influence on architecture and technology strategy across organizations.

Recognized technical contributions through patents, publications, or industry-defining innovation.

ACADEMIC CREDENTIALS

PhD or equivalent industry experience in Computer Engineering, Electrical Engineering, Computer Science, or a related field.

LOCATION: Santa Clara, CA

This role is not eligible for visa sponsorship.

#LI-TL1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

AMD is seeking a Fellow to lead the development of next-generation AI-native methodologies for silicon architecture, RTL generation, verification automation, and design optimization. This highly technical leadership role combines deep networking and ASIC architecture expertise with AI systems and scalable software infrastructure to transform field-proven programmable architectures into optimized fixed-function silicon. The Fellow will define strategy and drive innovation across AMD networking and infrastructure programs, influencing architecture, methodology, tooling, and engineering productivity.

The ideal candidate is a recognized technical leader in networking and silicon architecture with deep expertise across ASIC design, programmable packet processing, verification, and AI-assisted engineering. This individual will work across hardware and software organizations to est