FY27 Intern - Design For Test for a Secure Asynchronous IP - 6 months, Montbonnot

Location: Montbonnot, France Department: Interim Intern

Company:Qualcomm France S.A.R.L.

Job Area:Interns Group, Interns Group > Interim Intern

General Summary

The Qualcomm team in Montbonnot (France) is focusing on High-Assurance Security IPs for System-on-Chips (SoC). Composed of multiple profiles – Embedded Software, Hardware Design, Cryptography, Security, Certification – the team has been developing the TESIC IP, a Secure Enclave, composed of a proprietary CPU core, memories, analog security sensors, and crypto-accelerators. It is completed by a Software Development Kit (SDK). Both TESIC IP and TESIC SDK include security protections against physical attacks (Fault Injection and Side-Channel Attacks).

The internship will work within the Design team, to improve the test capabilities of the TESIC IP. This covers Memory Build-In Self-Test (MBIST), Design for Test (DFT), test coverage and fault analysis. Based on well-known tools, the intern will adapt them to the security context and the asynchronous logic specific features. The goal is to build a robust and efficient solution.

The intern will learn about design, design flow, security, in a global company, worldwide leader in Advanced Technologies.

Minimum Qualifications

Ongoing Master in Integrated Electronic Systems.

Preferred Qualifications

Knowledge of security for Embedded Systems.

Education/which semester and year of graduation

Internship for Master 2.

Location

Qualcomm Montbonnot

110 Rue Blaise Pascal

38330 Montbonnot-Saint-Martin

France

Internship Duration

Minimum 3 months, 6 months is preferred.

• References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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