Engineering intern for Cadence Tensilica CPU Processor Team in Cork, Ireland, focusing on RTL implementation of microprocessor cores, Verilog RTL, simulation and debugging, and EDA scripts to meet timing, area, and power goals.
What they are looking for
Verilog
Xtensa
Tcl
Perl
Shell
Details
- Work type
- Onsite
- Remote eligible
- No
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