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Intern: Application Engineering - Digital Verification & Simulation/VIP

Cadence Design Systems

Belo Horizonte · Posted Jun 09

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Intern: Application Engineering - Digital Verification & Simulation (VIP) in Belo Horizonte, Brazil. Internship focused on RTL-level verification, mentored in the System Verification Group (TFO-SVG), with exposure to Cadence Verification IP solutions and related tools. Responsibilities include providing technical support, developing test cases, running R&D fixes, and using TCL and Python for automation.

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