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Intern - Characterization and Support (Fall 2026)

Cadence Design Systems

San Jose · Posted Aug 29 · $40-$69/hr

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At a glance

Pay: $40-$69/hr
Location: San Jose, United States
Work type: Onsite
Start: Fall 2026

On-site Fall 2026 internship in San Jose, CA for a Post-Silicon Validation Engineering Intern in Cadence DDR IP group. Responsibilities include validating system-level and electrical performance of internal silicon test chips, debugging silicon issues, and delivering characterization reports.

What they are looking for

PythonRtlSignal integrityAnalog electronicsDigital electronics

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