On-site Fall 2026 internship in San Jose, CA for a Post-Silicon Validation Engineering Intern in Cadence DDR IP group. Responsibilities include validating system-level and electrical performance of internal silicon test chips, debugging silicon issues, and delivering characterization reports. Requires pursuing a Bachelor's or Master's in electrical engineering and ability to work full-time in San Jose during the Fall; local candidates preferred; must have legal authorization to work in the US.
What they are looking for
Details
- Work type
- Onsite
- Compensation
- Paid
- Remote eligible
- No
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