Intern - HBM SoC RTL Design Engineer

Intern - HBM SoC RTL Design Engineer at Micron in Folsom, CA. Six-month internship; design RTL for HBM SoC logic die, integrate internal and third‑party IP, collaborate with SoC architects to translate specifications into RTL, participate in SoC-level integration, and assist with pre‑ and post‑silicon validation. Requires pursuing a Bachelor’s or Master’s degree in electrical or computer engineering, cannot graduate prior to December 2027, and available for a 6‑month internship. Proficiency in SystemVerilog/Verilog; familiarity with RTL‑to‑GDS flow (synthesis, static timing analysis, sign‑off); experience with Cadence, Synopsys, and/or Siemens tools; programming or scripting experience (Python, TCL, Perl, or shell scripting). US base salary range is $38.84-$50.24 per hour, plus benefits.

What they are looking for

Details

Work type

Onsite

Compensation

Paid

Remote eligible

No