Join the Design Verification team as a junior or mid-level engineer to work on high-speed SerDes IP verification, DSP datapaths, and FW/HW joint verification, with exposure to AI-assisted engineering tools and a growth path.
What they are looking for
Systemverilog
Uvm
Python
Pcie
Ethernet
Details
- Work type
- Onsite
- Compensation
- Paid
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