PhD Intern in AI/ML & Design Automation at Marvell, Santa Clara, CA. Two tracks: Track 1 applies ML/AI to hardware and chip design (EDA automation, placement/routing, timing, power) using real design data; Track 2 focuses on enterprise AI tools (LLMs, agentic workflows, retrieval-augmented generation) integrated into Marvell's engineering workflows. Eligible applicants are enrolled PhD candidates in Computer Science, Electrical Engineering, or related fields with ML focus. Onsite internship in Silicon Valley with collaboration across hardware and software teams; involvement includes presenting research to leadership.
What they are looking for
Details
- Work type
- Onsite
Get new Engineering internships by email
Free daily digest, matched to what you pick. Unsubscribe anytime.
More Engineering internships
Mechanical Engineer Intern (Year-Round)
Charter Manufacturing · Saukville, WI
2027 Americas Region Industrial Engineering Summer Intern
UPS · Ups Corporate Offices, United States
Construction Intern
mydpr · Orlando, FL
Internship: Group Operations & Technology, Group Engineering – Wealth [January - May 2026]
OCBC Malaysia · OCBC Singapore
New Grad Civil Engineer I
HNTB · Houston, TX
Returning Intern Engineer- Structures- Summer 2027- Los Angeles Structures (For Current/Former HNTB Interns Only)
HNTB · Los Angeles, CA
More at Marvell Technology
Design For Test Intern, MS - Summer 2027
Santa Clara, CA
SRAM Circuit Design Intern, MS - Summer 2027
Burlington, VT
SRAM Software Engineer Intern, BS - Summer 2027
Burlington, VT
Design Verification Intern
2 Locations
System Chip Validation Intern
Petah-Tikva
Technical Sales Intern, BS - Summer 2027
Santa Clara, CA