Physical Design Engineer Intern (BS) Summer 2027 at Marvell in Santa Clara, CA. You will perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks using industry standard EDA tools (PrimeTime, Tempus). You will write scripts in Python, TCL, Perl, and Shell to aid design and development activities, and collaborate with RTL, Synthesis, and other Design teams to resolve congestion and timing bottlenecks while ensuring convergence and integration of designs.
What they are looking for
Details
- Work type
- Onsite
- Compensation
- Paid
- Remote eligible
- No
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