Physical Design Intern

Location: Singapore Department: Physical Design

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

Scope

We’re looking for a Physical Design Intern to join our SoC team and help design, tape out ultra low power chips in advanced process nodes. In this role, you’ll gain hands-on experience with physical implementation tools, learn how to deliver best PPA designs, and work alongside experienced engineers to tape out ultra low power products. This internship is an excellent opportunity to apply what you’ve learned in class, explore industry-standard tools, and see how your work connects to the technology powering everyday devices.

Responsibilities

As a Physical Design Intern, you will:

Support block-level physical implementation for SoC designs

Assist with floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure

Run and analyze static timing analysis (STA) and help debug timing violations (setup/hold)

Help perform power, signal integrity, and IR drop analysis under guidance

Contribute to design rule check (DRC) and layout versus schematic (LVS) closure activities

Develop and maintain scripts (e.g., Tcl, Python, Shell) to automate recurring tasks

Document methods, results, and learnings; present progress to your mentor and team

Collaborate with RTL, verification, and physical design engineers to resolve implementation issues

Basic Qualifications

Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

Completed coursework in several of the following areas:

Digital logic design

VLSI design / physical design / ASIC design

CMOS circuits

Computer architecture (preferred)

Familiarity with Verilog or VHDL and digital design concepts (timing, pipelining, clocking)

Basic understanding of physical design concepts such as placement, routing, timing closure, clock trees, and power grid planning

Comfortable working in a Linux/UNIX environment