Technical Lead - Fellow Hardware Engineer, NPU

Location: Mountain View, CA Department: Hardware Platform Development

We are CARIAD, an automotive software development team with the Volkswagen Group. Our mission is to make the automotive experience safer, more sustainable, more comfortable, more digital, and more fun. To achieve that we are building the leading tech stack for the automotive industry and creating a unified software platform for over 10 million new vehicles per year. We’re looking for talented, digital minds like you to help us create code that moves the world. Together with you, we’ll build outstanding digital experiences and products for all Volkswagen Group brands that will transform mobility. Join us as we shape the future of the car and everyone around it.

We are CARIAD, an automotive software development team with the Volkswagen Group. Our mission is to make the automotive experience safer, more sustainable, more comfortable, more digital, and more fun. To achieve that we are building the leading tech stack for the automotive industry and creating a unified software platform for over 10 million new vehicles per year. We’re looking for talented, digital minds like you to help us create code that moves the world. Together with you, we’ll build outstanding digital experiences and products for all Volkswagen Group brands that will transform mobility. Join us as we shape the future of the car and everyone around it.

​Role Summary

The Fellow and Technical Lead, NPU serves as CARIAD’s senior technical authority for automotive neural processing unit (NPU) architecture, microarchitecture and integration into the system-on-chip (SoC). The role provides advanced architectural leadership, influences critical technical decisions across the NPU and broader SoC development environment, and translates AI workloads and product requirements into NPU designs. The Fellow is responsible for leading technical execution through validation and production readiness, applying deep SoC architecture experience to ensure the NPU operates effectively within the complete SoC. As technical team lead, the Fellow provides architectural direction and technical leadership across the NPU engineering disciplines, including architecture, machine learning, compiler and toolchain, hardware design, RTL, design verification, FPGA, embedded software and technical program coordination. The role is accountable for delivering an NPU product that meets agreed functionality, performance, power, quality and schedule targets, including successful SoC integration. The Fellow exercises significant technical influence across participating engineering teams and development partners while operating within established product, program, and organizational decision-making structures.

Role Responsibilities

Technical Lead Responsibilities

Serve as the senior technical authority for NPU design, architecture, interfaces, and key implementation decisions; evaluate and challenge architectural assumptions, recommend changes to the broader SoC architecture where warranted, and align significant cross-domain decisions with appropriate SoC and engineering leadership.

Align NPU solutions with product, platform and vehicle requirements, including applicable safety, security and quality constraints.

Translate AI workload and product requirements into NPU designs and SoC integration plan

Lead NPU architecture, design and code reviews; approve technical proposals and changes within the role's defined authority; and provide expert recommendations on major architectural changes requiring broader engineering alignment or approval.

Identify, communicate and mitigate NPU performance, implementation and integration risks; escalate cross-domain dependencies.

Act as the NPU technical interface to SoC engineering, technical program management, software, safety, security, quality and development partners.

Set technical standards for modeling, design, verification, software quality and documentation across the NPU team.

Direct and coordinate the NPU team’s technical work, resolve cross-functional issues and ensure that team deliverables meet product requirements.

Provide independent technical assessments and recommendations to senior engineering leadership on critical NPU architecture decisions, significant design tradeoffs, and technical risks with implications for SoC performance, integration, or product delivery.

NPU Architechture and SoC Integration Execution

Define and lead the NPU architecture and technical roadmap for automotive AI workloads, exercising independent architectural judgment and influencing the overall SoC strategy through recommendations on performance, scalability, integration, and technology tradeoffs.

Own NPU product delivery from architecture through RTL, verification, SoC integration and post-silicon validation; align milestones and dependencies with technical program management.

Define NPU and supporting IP requirements and technical criteria for supplier evaluation and selection.

Own NPU architecture and behavior specifications, including compute, memory, dataflow, interfaces and integration requirements.

Define supported AI use cases, numerical precision, performance targets and acceptance criteria with product and software teams.

Provide technical leadership across SoC, RTL, physical design and software disciplines to evaluate and resolve complex architecture and implementation tradeoffs, challenge technical assumptions, and influence cross-domain decisions affecting NPU and SoC performance.

Lead technical evaluation of NPU-related IP, technology alternatives, and engineering partners; provide authoritative technical recommendations influencing architecture selection, supplier decisions, and technical scope, while supporting Procurement on licensing and commercial considerations.

Define NPU integration requirements for NoC, memory, clocks, resets, power management, interrupts, safety and security.

Model NPU and full-SoC performance, bandwidt