ASIC Physical Design Engineer intern at NVIDIA in Taiwan's Hsinchu RDSS program. Role covers RTL frozen to tape-out including synthesis, formal verification, constraints, timing closure, floorplanning, and flow automation; requires MS in EE or Microelectronics and hands-on experience with EDA tools (Synopsys: DC/PT/Formality; Cadence: RC Compiler/LEC).
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- Work type
- Onsite
- Remote eligible
- No
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