Fellow, Server CPU Validation Architect

Location: Santa Clara, California, United States Department: Engineering

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Fellow, Server CPU Validation Architect

THE TEAM

Our Server Platform Solutions Engineering team is responsible for ensuring the quality, reliability, and security of every server product we deliver. The team partners closely with design, product engineering, software, and hardware organizations from concept through post-launch, driving validation strategy, silicon bring-up, debug, automation, and test infrastructure. They play a critical role in achieving product readiness, enabling customer use cases, and maintaining the highest quality standards.

THE PERSON

The Fellow-level Server CPU Validation Architect combines deep technical expertise with strong business acumen and experience leading global validation efforts. This individual brings extensive knowledge of server CPU architecture, post-silicon validation methodologies, and program ownership, while demonstrating exceptional communication, decision-making, and leadership skills. A customer-focused mindset, passion for continuous improvement, and ability to influence at the executive level are essential.

THE ROLE

Drive CPU validation strategy, test planning, and execution across next-generation server platforms.

Lead development of validation methodologies, tools, and frameworks to identify architectural, design, and manufacturing issues.

Partner with technical leaders to validate emerging technologies including PCIe, CXL, and coherent interconnects.

Define large-scale validation and emulation strategies to maximize product quality and accelerate deployment.

Drive automation requirements and AI-enabled solutions to improve validation efficiency, debug capabilities, and time-to-market.

Serve as the technical leader for complex system-level debug challenges spanning hardware and software.

Champion innovation, process improvements, and best practices across the validation organization.

EXPERIENCE

Understanding of modern x86 CPU and server platform architectures

Multiple years of experience developing validation methodologies, infrastructure, and test plans

Experience with multiple silicon bring-ups and driving it to production along with debug experience and best practices

Strong system-level and SoC debug skills

Programming and scripting experience (e.g. C/C++, Python)

Working knowledge of Linux and Windows server operating systems

AI first approach to problem solving and demonstrated experience of using AI for test plan, test content, test execution and debug.

Strong analytical, communication, and cross-functional collaboration skills

Self-motivated with the ability to drive results independently

EDUCATION

Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science required; Master’s degree preferred.

LOCATION

Austin, TX

Santa Clara, CA

Folsom, CA

This role is not eligible for visa sponsorship.

#LI-LM1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

Our Server Platform Solutions Engineering team is responsible for ensuring the quality, reliability, and security of every server product we deliver. The team partners closely with design, product engineering, software, and hardware organizations from concept through post-launch, driving validation strategy, silicon bring-up, debug, automation, and test infrastructure. They play a critical role in achieving product readiness, enabling customer use cases, and maintaining the highest quality standards.

The Fellow-level Server CPU Validation Architect combines deep technical expertise with strong business acumen and experience leading global validation efforts. This individual brings extensive knowledge of server CPU architecture, post-silicon validation methodologies, and program ownership, while demonstrating exceptional communication, decision-making, and leadership skills. A customer-focused mindset, passion for continuous improvement, and ability to influence at the executive level are essential.

Drive CPU validation strategy, test planning, and execution across next-generation server platforms.

Lead development of validation methodologies, tools, and frameworks to identify architectural, design, and manufacturing issues.

Partner with technical leaders to validate