FY27 Intern- Integration of a RISC-V CPU into a Cache-Coherent Emulation Platform - Sophia, 6 months

Location: Bainbridge, Alpes-de-Haute-Provence, France Department: Interim Intern

Company:Qualcomm France S.A.R.L.

Job Area:Interns Group, Interns Group > Interim Intern

General Summary

You will join the emulation team developing a CPU-based platform built around a memory interconnect. This platform is used to verify interoperability between key system IPs, including CPUs, the network-on-chip (NoC), and DDR controllers. It also supports their characterization and performance validation. The complete system will be mapped onto hardware emulators such as Palladium or Veloce.

Internship Description

The internship will take place at Qualcomm France’s R&D NoC technology center in Sophia Antipolis, within an office of approximately 50 engineers.

The primary objective is to integrate Qualcomm latest RISC-V CPU into the emulation team existing RTL platform and connect it to a cache-coherent interconnect. The intern will reuse or develop boot code in C or assembly for execution on the CPU and integrate the RISC-V toolchain into the existing software build flow.

The resulting RTL platform will first be compiled and validated using an RTL simulator, such as VCS or ModelSim, to debug the CPU integration and boot code. Finally, the platform will be compiled for Palladium or Veloce hardware emulators, enabling the development and execution of additional test cases on the RISC-V CPU.

Progress of Internship

Initial Training

Understand the emulation team’s scope, constraints, and requirements, including testbench implementation, system validation, test case execution, and hardware emulation.

Gain a good understanding of Qualcomm interconnects and how they interact with other system IPs.

RISC-V architecture study

Core Activities

Collaborate with the CPU team to import and compile the RISC-V CPU RTL.

Integrate the RISC-V CPU and interconnect into the emulation testbench used for the current mobile project.

Develop or reuse boot code for the RISC-V CPU.

Integrate the RISC-V toolchain into the existing software build flow.

Run RTL simulations to validate and debug the CPU integration and C boot code.

Compile the platform for a Palladium or Veloce hardware emulator, then validate and debug the CPU integration and boot-code execution.

Bonus

Port the emulation team’s complete suite of Arm-based C test cases to the RISC-V platform and run them in hardware emulation.

Skills/Requirements

Internship duration is 6 months

Master’s degree in Microelectronics, Computer Science, or related field

Experience with Verilog (preferably), or VHDL

Ability to quickly react and adapt to changes

Excellent communication skills, oral and written, French and English

You will be part of one the advanced R&D center in Qualcomm, with the most competitive salary in the industry.

Keywords: RISC-V, CPU integration, SoC, RTL, Verilog, hardware emulation, cache coherency, Network-on-Chip (NoC), C/assembly, boot code, Palladium, Veloce.

• References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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