On-site internship role in San Jose, California within the Cadence DDR IP group as a Post-Silicon Validation Engineering Intern. Responsible for validating system-level and electrical performance of internal silicon test chips; debugging silicon issues with analog and digital design teams; delivering characterization reports; cross-functional collaboration to ensure product functionality and reliability. Requires pursuing a Bachelor's or Master's in electrical engineering; local candidates preferred; able to work full-time in San Jose during Fall 2026; must have US work authorization. Salary: $40-$69 per hour; incentive compensation possible (bonus, equity, and benefits).
What they are looking for
Details
- Work type
- Onsite
- Compensation
- Paid
- Remote eligible
- No
Get new internships by email
Free daily digest, matched to what you pick. Unsubscribe anytime.
More Other internships in San Jose
Intern
Ap · Bloomington, MN
Intern
Ap · Fargo, ND
Surgical Tech Extern, OR Baptist, PRN
Prisma Health · Columbia, SC
Inspector Apprentice (Manheim)
Cox Enterprises · Bordentown, NJ
Development Intern - NJ
rockefellergroup · Morristown, NJ
Development Intern - Northeast
rockefellergroup · NY, United States
More at cadence
Intern Digital Implementation
Velizy
Graduate Student Intern - Software Engineering
Austin, United States
Intern on AMS tool in Milan
Milan, Italy
Intern in Photonics flow
Meylan 01
Analog/Mixed-Signal IC Design Co-Op/Intern (Summer 2026) / Stage/Co-Op en Conception de CI Analogiques/Signal Mixte (Été 2026)
Mount-Royal
Software Intern
San Jose, United States