Intern - Engineer, Region E

Location: Fab 10N/X, Singapore

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Location

Singapore

Department

Advanced NAND Process Development

Project Title

Elimination of Wafer-Edge Coating in the Pillar Module

Project Description

The Pillar module applies a sacrificial wafer-edge coating before high-aspect-ratio patterning to mitigate wafer-edge arcing. While effective, this coating adds process steps, cycle time, and consumable costs.

An ongoing engineering evaluation within the Wafer Edge Region Process Development team has demonstrated that the coating can be removed from a limited wafer population without process excursions. This internship project represents the next phase of that evaluation.

Working under the guidance of experienced process development engineers, the intern will expand the existing dataset and analytical framework to address the remaining technical questions before a permanent process change can be approved. The project will provide practical exposure to experimental design, semiconductor process integration, wafer-edge characterization, statistical analysis, and AI-enabled engineering workflows.

Objective of the Project

Compare wafer-edge defect performance between coated and coating-free wafers.

Determine whether removing the coating increases wafer-edge arcing in downstream process modules and, if so, identify its origin.

Develop a safe and systematic approach for increasing the run rate of coating-free wafers.

Establish the inline monitoring criteria and process margins required to enable full conversion to a coating-free process.

Opportunities for Full-Time Employment

This project closely reflects the responsibilities of a Wafer Edge Region and Uniformity Process Development Engineer. These include designing experiments, collecting and analyzing data, distinguishing genuine process effects from confounding variables, understanding integration and structural constraints at the wafer edge, and presenting data-driven recommendations during technical reviews.

The intern will work directly with the engineering owners of the module and gain hands-on experience in a production development environment.

Interns who demonstrate strong engineering judgment, rigorous data analysis, and ownership of their deliverables may be considered for graduate Process Development Engineer opportunities within NAND Process Development in Singapore, subject to business requirements, position availability, and the applicable selection process.

The intern will also complete a well-documented wafer-edge process development project that can serve as a reference for future career opportunities.

Project Scope

Develop an understanding of the general process flow for three-dimensional NAND memory and where the Pillar module and its edge-protection step are positioned within the process.

Examine why edge protection is used before high-aspect-ratio etching and how film stress, adhesion, and edge profiles contribute to peeling and particulate defects at the wafer bevel and backside.

Learn wafer-edge, bevel, and backside inspection techniques, as well as relevant defect-classification conventions.

Observe defect-review and cross-section characterization sessions with the engineering team to connect defect signatures to their physical origins.

Apply statistical methods, including design of experiments, hypothesis testing, variance decomposition, and correlation analysis, while recognizing potentially confounded comparisons such as calendar effects, tool mix, and lot mix.

Learning Opportunities

Gain practical exposure to semiconductor process development, process integration, wafer-edge engineering, metrology, and defect characterization.

Develop experience in distinguishing process effects from confounding variables within large and imperfect manufacturing datasets.

Learn to use approved Artificial Intelligence tools, including Microsoft 365 Copilot and Claude, to generate and refactor analysis code, summarize technical information, and draft report content.

Strengthen technical writing, presentation, and cross-functional collaboration skills through engagement with process owners and engineering stakeholders.

Deliverables

A validated comparison of wafer-edge defects and arcing performance between coated and coating-free wafers.

A statistically defensible data package addressing process performance, technical risks, process margins, and relevant confounding variables.

Recommended inline monitoring criteria and a systematic plan for increasing the run rate of coating-free wafers.

Reproducible analysis tools, documented methodologies, and a final technical presentation summarizing the findings and recommendations.

Impact of the Project

Process simplification: Validated removal of the wafer-edge coating would reduce the number of process steps in the Pillar module, shorten cycle time, and reduce consumable usage.

Defect and uniformity improvement: Removing the coating may eliminate defect and uniformity signatures associated with the coating boundary. The project will quantify these effects rather than assume them.

Improved decision quality: The data package will convert an initial feasibility observation from a limited wafer population into a statistically defensible basis for a permanent process change, including the wafer-edge margin evidence required by the relevant module owners.

Lasting analytical capability: The analysis tools and monitoring criteria developed through the project may remain in use by th