Develop digital sub-circuits for SOCs using Verilog/SystemVerilog (RTL, synthesis, STA), DFT, and formal verification; collaborate with analog, mixed-signal, and software teams to optimize interfaces and performance; participate in post-silicon validation and documentation; based in Catania, Italy with an estimated gross annual base salary of €38,000–€52,300 and potential total compensation elements such as incentives or equity.
What they are looking for
Details
- Work type
- Onsite
- Compensation
- Paid
- Remote eligible
- No
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