TOP Design Verification Engineer Intern at SK Hynix Memory Solution America in San Jose. 6-month internship, 40 hours/week, start Sep/Oct 2026. Responsibilities include studying the SOC TOP microarchitecture, listing verification requirements, modifying the test bench, creating/modifying test cases, debugging and filing bug reports, and achieving functional and toggle coverage. Minimum requirements: BSEE/MSEE or related field; Digital IC design & verification; Windows and Linux; Python or Perl scripting; SystemVerilog, UVM, C/Assembly; Perforce and Confluence; familiarity with UCIe, CPU architecture, NAND protocols; compensation $35-$45/hr.
What they are looking for
Details
- Work type
- Onsite
- Compensation
- Paid
- Remote eligible
- No
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